1. Field of the Invention
The present invention relates generally to circuit techniques, and more specifically, to a memory cell.
2. Related Art
Static random-access memory (SRAM) is an important type of memory. Typical SRAM configuration includes an SRAM cell and a sense amplifier. An SRAM cell is a basic unit in SRAM chip for storing logic values. SRAM cell itself has a limited driving ability, which cannot meet the requirement for driving post stage logic circuits. A sense amplifier is employed for processing signals outputted from SRAM cell. A sense amplifier is capable of driving post stage logic circuits due to its stronger driving ability. A sense amplifier usually is multiplexed by a plurality of SRAM cells.
FIG. 1 is a structure of a conventional SRAM cell, in which, logic values are stored in a circuit consisting of M1, M2, M3 and M4 and this part forms a core memory circuit. WWL is used for controlling transistors M5 and M6 to select the SRAM cell for performing a write operation. WBL and /WBL are used for inputting to the SRAM cell a value to be written. This part forms a write-related circuit. RWL is used for controlling transistor M8 to select the SRAM cell for performing a read operation. RBL is used for reading out values stored in the SRAM cell. If the values stored in the SRAM cell correspond to producing a low level on RBL, M7 is turned on by a high level at an output node NC of the core memory circuit. If the values stored in the SRAM cell correspond to producing a high level on RBL, M7 is cut off by a low level at the node NC. This part forms a read-related circuit.
In the above-described structure, RBL is pre-charged to a high level. That is to say, RBL is always at a high level unless a low level needs to be outputted. During a read operation, pre-charging RBL is stopped. Then, M8 is turned on by a high level on RWL, so as to select the SRAM cell. In the case where M7 is also turned on, a path is formed from RBL to a reference level, so as to pull down the level on RBL from a high level to a low level.
After the read operation is finished, M8 is cut off by the low level on RWL and the pre-charge circuit is re-connected to RBL, and thus RBL resumes a high level. When M7 is cut off, there is no path formed between RBL and the reference level, and thus RBL still maintains a high level. When the read operation is finished, M8 is cut off by the low level on RML and the pre-charge circuit is re-connected to RBL, which is still at a high level.
One of ordinary skill in the art can understand that, even if the transistor is in an OFF state, there exists a weak current flowing between a source and a drain because of a potential difference between the source and the drain of the transistor. This weak current is referred to as leakage current. This leakage current is related to the potential difference between a source and a drain as well as related to the dimension of a transistor channel. In order to make RBL switch rapidly from a high level to a low level when a low level needs to be outputted, M8 usually has a relatively large dimension of channel for rapidly forming a path from RBL to reference level.
However, the large dimension of M8 means a relatively large leakage current existing in M8. As described above, whether M7 is turned on depends on logic values stored in the SRAM cell. Assumed that the probabilities of having logic value 0 stored in SRAM cell and having logic value 1 stored in SRAM cell both are 50%, M7 is in an ON state for half the time.
Accordingly, within half the working time of the SRAM cell, there is a relatively large leakage current flowing from RBL to reference level. Although the leakage current is much smaller than working current, its influence on power consumption cannot be ignored since it always exists.
Therefore, a new technical solution is desirable for improving leakage current performance of SRAM cell.